1. Field of the Invention
The present invention relates generally to methods for fabricating microelectronic fabrications. More particularly, the present invention relates to methods for fabricating high areal density patterned microelectronic structures within microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed in part from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
As microelectronic fabrication integration levels have increased and microelectronic device and patterned microelectronic conductor layer dimensions have decreased, it has become increasingly more difficult within the art of microelectronic fabrication to fabricate within microelectronic fabrications patterned microelectronic structures with enhanced areal density. Particularly difficult within the art of microelectronic fabrication to fabricate with enhanced areal density, in particular while maintaining comparatively high levels of areal capacitance, are microelectronic structures employed within microelectronic capacitors employed within dynamic random access memory (DRAM) cells employed within semiconductor integrated circuit microelectronic fabrications.
It is thus towards the goal of forming within the art of microelectronic fabrication patterned microelectronic structures, such as but not limited to patterned microelectronic structures which are employed within microelectronic capacitors employed within dynamic random access memory (DRAM) cells within semiconductor integrated circuit microelectronic fabrications, with enhanced areal density, that the present invention is directed.
Various methods have been disclosed within the art of microelectronic fabrication for forming patterned microelectronic structures with desirable properties within the art of microelectronic fabrication.
For example, Koh, in U.S. Pat. No. 5,364,813, discloses a method for forming from a blanket polysilicon capacitor plate layer for use within a semiconductor integrated circuit microelectronic fabrication a patterned polysilicon capacitor plate layer for use within a polysilicon capacitor for use within the semiconductor integrated circuit microelectronic fabrication, while avoiding the formation of polysilicon etch residues when forming from the blanket polysilicon capacitor plate layer the patterned polysilicon capacitor plate layer. To realize the foregoing object, the method employs an in-situ oxidation of an unneeded portion of the blanket polysilicon capacitor plate layer from which is formed the patterned polysilicon capacitor plate layer, to form therefrom a silicon oxide dielectric layer, rather than an etch patterning of the blanket polysilicon capacitor plate layer when forming the patterned polysilicon capacitor plate layer.
In addition, Wu, in U.S. Pat. No. 5,650,351, discloses a method for forming, for use within a microelectronic fabrication, a microelectronic capacitor, such as a microelectronic capacitor employed within a dynamic random access memory (DRAM) cell, wherein a patterned capacitor plate layer within the microelectronic capacitor has multiple pillars which provide for an enhanced areal capacitance of the microelectronic capacitor. To realize the foregoing object, the method employs an oxidized hemispherical grain silicon (HSG) layer as a masking layer when forming the patterned capacitor plate layer within the microelectronic capacitor.
Further, Lien et al., in U.S. Pat. No. 6,022,776, discloses a method for forming within a semiconductor integrated circuit microelectronic fabrication a plurality of contact vias of varying depths through a series of dielectric layers of varying thicknesses, while avoiding when forming the plurality of contact vias overetching into a semiconductor substrate which is employed for forming the semiconductor integrated circuit microelectronic fabrication. To realize the foregoing object, the method employs a silicon oxynitride etch stop layer formed upon the semiconductor 5 substrate at the location of a series of deeper contact vias, such that there is avoided at the location of the series of deeper contact vias overetching into the semiconductor substrate when forming the plurality of contact vias through the series of dielectric layers.
Still further, Chien et al., in U.S. Pat. No. 6,030,867, discloses a method for forming, with enhanced areal capacitance, a microelectronic capacitor for use within a dynamic random access memory (DRAM) cell within a semiconductor integrated circuit microelectronic fabrication. To realize the foregoing object, the method employs, in conjunction with other features, a hemispherical grain silicon (HSG) layer as an etch mask layer when forming a patterned capacitor plate layer within the microelectronic capacitor.
Finally, Jeng et al., in U.S. Pat. No. 6,037,211, discloses a method for forming through a dielectric layer within a semiconductor integrated circuit microelectronic fabrication a contact via having a high aspect ratio, where the contact via having the high aspect ratio is formed with an enhanced process margin. In order to realize the foregoing object, the method employs a multiple etch method which in part is a self-aligned etch method, when forming the contact via having the high aspect ratio.
Desirable in the art of microelectronic fabrication are additional methods and materials which may be employed for forming within microelectronic fabrications patterned microelectronic structures, such as but not limited to patterned microelectronic structures which are employed within microelectronic capacitors employed within dynamic random access memory (DRAM) cells, with enhanced areal density.
It is towards the foregoing object that the present invention is directed.